Apply For Lead Hardware Engineer - DFT IP R&D

• Cadence Design Systems
• Office Location
• Full Time

Experience: 4 - 4 years required

Pay:

Salary Information not included

Type: Full Time

Location: Noida

Skills: RTL design, Computer architecture, Verification, Placement, static timing analysis, Power analysis, Routing, Extraction, optimization, Verilog, SystemVerilog, UVM, Perl, Python, Data structures, algorithms, synthesis, STA, DFT architecture, RTL compilation, EDA tool development