Apply For FPGA Design Engineer

• Agiliad
• Office Location
• Full Time

Experience: 4 - 4 years required

Pay:

Salary Information not included

Type: Full Time

Location: Maharashtra

Skills: VHDL, Verilog, System Verilog, RTL design, FPGA Design, Lattice, timing analysis, Debugging, Troubleshooting, Communication protocols, UART, SPI, AMBA, AXI, flash, Ethernet, Serdes, DDR, hardware debugging, Interpersonal Skills, Communication skills, presentation skills, FPGA design tools, FPGA architecture, Altera FPGA families, Verificationsimulation tools, code optimization, Synthesis reports, FPGA design constraints, Bus interfaces, Memories, Analog fundamentals, digital fundamentals, Oscillator, Logic analysers, Low power consumption, programming skills, Hardware description languages, Problemsolving, Collaboration Skills