Apply For Engineer, ASIC Design

• kinara
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: VLSI design, SOC, synthesis, LEC, Lint, CDC, CLP, UPF, Verilog, VHDL, SystemVerilog, power optimization, Performance optimization, Simulation, Debugging, Python, Perl, IP design, Design Debug, Timing clean up, Area Optimization, Test bench development, Processor subsystem design, interconnect design, High speed IO interface design, Tcl