Apply For ASIC/RTL Design Engineer - Sr Lead/Staff

• Qualcomm
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: bus protocols, Formal Verification, Perl, Communication skills, digital front end design, RTL microarchitecture, VerilogSV, low power design methodology, clock domain crossing designs, RTL to GDS flow, Spyglass LintCDC checks, mobile MultimediaCamera design, DSPISP knowledge, TCL language, postSi debug, Documentation Skills, unit level test plan, team working attitude