Apply For ASIC SoC Design Engineer

• Google
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: RTL Coding, Verilog, SystemVerilog, Lint, synthesis, UPF, Interconnects, Security, Interrupts, ASIC design methodologies, CDCRDC, Design for testing, ATPGMemory BIST, Low Power OptimizationEstimation, Process Cores, DEBUG, Trace, ClocksReset, PowerVoltage Domains, PinMux