Apply For ASIC RTL (DSP) Design Engineer/Sr Lead/Staff/Sr Staff

• Qualcomm
• Office Location
• Full Time

Experience: 1 - 1 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: RTL design, Verilog, System Verilog, VHDL, AXI, APB, AHB, SystemC, C, Spyglass, ASIC design, scripting languages, Synopsys DCG, Cadence Genus, SVA assertions, RTL to gates synthesis