Apply For ASIC RTL Design Manager, Silicon

• Google
• Office Location
• Full Time

Experience: 15 - 15 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog, System Verilog, Microarchitecture, Interconnects, RTL design, ASIC RTL design, ARMbased SoCs, ASIC methodology, IP Development, interconnect IP design