Apply For ASIC RTL Design Engineer, Silicon

• Google
• Office Location
• Full Time

Experience: 2 - 2 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: RTL design, Verilog, System Verilog, Microarchitecture, Lint, CDC, timing closure, synthesis, ARMbased SoCs, ASIC methodology, RTL quality checks, low power estimation