Apply For ASIC RTL Design Engineer -

• Qualcomm
• Office Location
• Full Time

Experience: 2 - 2 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: ASIC design, RTL Coding, Verilog, VHDL, SystemVerilog, bus protocols, AHB, AXI, NOC, Formal Verification, DFT, mobile Multimedia, DSP, ISP, Perl, low power design methodology, clock domain crossing designs, Spyglass Lint, CDC checks, Cadence LEC, RTL to GDS flow, PD teams, Camera design, Tcl, postSi debug, Documentation Skills, unit level test plan