Apply For ASIC Engineer, RTL Integration

• Google
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog, System Verilog, Microarchitecture, Automation, Lint, synthesis, timing closure, Interconnects, Security, Interrupts, RegisterTransfer Level RTL design, Clock Domain Crossing, Reset Domain Crossing, IP integration methodology, IP design, ARMbased SoCs, ARMprotocols, ASIC methodology, low power estimation, DEBUG, Trace, ClocksReset, PowerVoltage Domains, Pin Multiplexing