Apply For ASIC Design Engineer, Silicon

• Google
• Office Location
• Full Time

Experience: 6 - 6 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Python, Perl, Lint, CDC, RDC, timing closure, synthesis, ARMbased System on a chip SoCs, ASIC methodology, RegisterTransfer Level RTL design, VerilogSystem Verilog, Intellectual Property IP design, low power estimation