Apply For ASIC Design Engineer, RTL, Silicon

• Google
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: Verilog, SystemVerilog, UPF, Interconnects, Security, Interrupts, ASIC design methodologies, DFT ATPGMemory BIST, low power estimation, chip design flow, STA Closure, DV testplan review, Coverage analysis, Processor Cores, DEBUG, Trace, ClocksReset, PowerVoltage Domains, Pinmuxing