Apply For ASIC Design Engineer

• Axiado
• Office Location
• Full Time

Experience: 8 - 8 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: Verification, synthesis, Verilog, scripting languages, RTL logic design, timing optimization, microarchitecture specifications, soc integration, interface protocols, FPGA based emulation platforms, Tapeout, Silicon bringup, DEBUG, repository management tools, Bug Tracking Tools