VLSI Design Set 2

Which among the following is/are regarded as an/the active resistor/s?

In testability, which terminology is used to represent or indicate the formal evidences of correctness?

Which among the following is regarded as an electrical fault?

Which among the following faults occur/s due to physical defects?

In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.

Which level of system implementation includes the specific function oriented registers, counters & multiplexers?

Which among the following is/are taken into account for post-layout simulation?

Which among the following operation/s is/are executed in physical design or layout synthesis stage?

In VHDL, which class of scalar data type represents the values necessary for a specific operation?

Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?