Mixed Signal Design Set 3

In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.

In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output.

For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS.

In MOS devices, the current at any instant of time is ______of the voltage across their terminals.

On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics?

An ideal op-amp has ________

Stuck open (off) fault occur/s due to _________

Which type/s of stuck at fault model exhibit/s the reduced complexity level of test generation?

Why is multiple stuck-at fault model preferred for DUT?

Which among the following EDA tool is available for design simulation?