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1.
Which among the following is/are regarded as an/the active resistor/s?
2.
In testability, which terminology is used to represent or indicate the formal evidences of correctness?
3.
Which among the following is regarded as an electrical fault?
4.
Which among the following faults occur/s due to physical defects?
5.
In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.
6.
Which level of system implementation includes the specific function oriented registers, counters & multiplexers?
7.
Which among the following is/are taken into account for post-layout simulation?
8.
Which among the following operation/s is/are executed in physical design or layout synthesis stage?
9.
In VHDL, which class of scalar data type represents the values necessary for a specific operation?
10.
Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?