Microprocesssor Set 3

CPU ✘ ALU ✘ Both A and B ✘ None of these ✔

Interrupt ✘ Transfer ✘ Both A and B ✘ None of these ✔

INTR ✘ TRAP ✘ RST6.5 ✘ None of these ✔

Select Interrupt Mask ✘ Sorting Interrupt Mask ✘ Set Interrupt Mask ✘ None of these ✔

The write operation is done or not ✘ The interrupt is Masked or not ✘ Both A and B ✘ None of these ✔

Bus interface unit ✘ Bess interface unit ✘ Both A and B ✘ None of these ✔

Instruction pointer ✘ Instruction purpose ✘ Instruction paints ✘ None of these ✔

Physical ✘ Logical ✘ Both A and B ✘ None of these ✔

Deal inline package ✘ Dual inline package ✘ Direct inline package ✘ Digital inline package ✔