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1.
A 32 bit adder is formed by cascading 4 bit CLA adder. The gate delays (latency) for getting the sum bits is
2.
The threshold level for logic 1 in the TTL family is
3.
An N-bit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator). The minimum addition time using the best architecture for this adder is
4.
A multiplexor with a 4-bit data select input is a
5.
The number of fill and half-address required to add 16-bit number is:
6.
The following circuit implements a two-input AND gate using two 2-1 multiplexers. What are the values of X1, X2, X3 ?
7.
The complement of the function F = (A + B’)(C’ + D)(B’ + C) is:
8.
Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________ [This Question was originally a Fill-in-the-blanks Question]
9.
Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is
10.
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is