Computer Science GATE- Digital Logic Set 2

In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be _____ on the rising edge of the clock.

Which of the following is a sequential circuit?

In a three stage counter, using RS flip flops what will be the value of the counter after giving 9 pulses to its input? Assume that the value of counter before giving any pulses is 1.

A modulus -12 ring counter requires a minimum of

The functional difference between SR flip-flop and JK flip-flop is that

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation ?

Consider the following statements regarding counters:
S1 : The Hamming distance of an Overbeck counter is 1 and the Hamming distance of a Johnson counter is 2.
S2 : Only output sequence 0, 8, 12, 14, 15, 7, 3, 1, 0, ... is possible in Overbeck counter but not output sequence 2, 1, 8, 4, 2, 1, ...
S3 : A binary counter can represent 2^N states, where N is the number of bits in the code, whereas an Overbeck counter can represent only N states and a Johnson counter can represent only 2N states.

How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is   Note : This question was asked as Numerical Answer Type.

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,...) is ________