1.
The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.
2.
Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?
3.
_________ is the fundamental architecture block or element of a target PL
4.
In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?
5.
Among the VHDL features, which language statements are executed at the same time in parallel flow?
6.
In Net-list language, the net-list is generated _______synthesizing VHDL code.
7.
In VHDL, which object/s is/are used to connect entities together for the model formation?
8.
Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature?
9.
Which type of simulation mode is used to check the timing performance of a design?
10.
In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?