CMOS design Set 1

The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.

Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?

_________ is the fundamental architecture block or element of a target PL

In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?

Among the VHDL features, which language statements are executed at the same time in parallel flow?

In Net-list language, the net-list is generated _______synthesizing VHDL code.

In VHDL, which object/s is/are used to connect entities together for the model formation?

Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature?

Which type of simulation mode is used to check the timing performance of a design?

In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?