Staff Verification Quest Global
Quest Global
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: Kerala
Skills: SystemVerilog, UVM, ASIC Verification, RTL, synthesis, STA, DFT, JIRA, Python, SYNOPSYS, Cadence simulation tools, Gate level debug, Formal Equivalence tools, PLLs, mixedsignal design modelling
About Quest Global
Job Description
The ideal candidate for this role will be an RTL engineer with over 8 years of practical design and verification experience using SystemVerilog UVM and ASIC verification. You should have hands-on experience with Synopsys and/or Cadence simulation tools, as well as proficiency in RTL and possibly Gate level debug. Desirable skills for this position include experience with Synopsys and/or Cadence Synthesis, STA, DFT, Formal Equivalence tools, and familiarity with JIRA. It would be beneficial to have knowledge of scripting languages such as Python or equivalent, understanding of PLLs, and experience with mixed-signal design modelling and debugging. Keywords: UVM, RTL, SystemVerilog, Synthesis, Analog.,