Sr. Analog Layout Engineer Eximietas Design
Eximietas Design
Office Location
Full Time
Experience: 7 - 7 years required
Pay:
Salary Information not included
Type: Full Time
Location: Andhra Pradesh
Skills: Electromigration, scripting languages, Perl, Communication skills, IR drop, selfheating, RC delay, parasitic capacitance optimization, Cadence, SYNOPSYS, SKILL
About Eximietas Design
Job Description
Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross-functional teams are also key to success in this role. If you are interested in this opportunity or know someone suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are looking forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design. Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,