Signal Integrity Engineer HCLTech

About HCLTech

Job Description

You should have 4 to 10 years of experience with a strong knowledge of Signal Integrity and Power Integrity fundamental concepts. Strong experience in PCB modeling is required. You will be responsible for performing Transmission line & Via modeling and carrying out experiments to validate modeling outcomes and methodologies. A deep understanding of S-parameter & its modeling concepts for Single-ended and differential interfaces is essential. Experience in simulating (FD/TD) memory interfaces for Board (DDR4/LPDDR4/DDR5/LPDDR5) and High-Speed Serial IO interfaces for Board and Package (PCIe Gen3/4, USB3/3.1, and MIPI CSI/DSI Interfaces, etc.) is required. You will be involved in system-level simulation for Read & Write cases for eMMC/NAND Flash/SDIO and HDMI signals with connectors & cable including CMC for all PVT corners. Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time-domain Analysis is expected. Power Integrity Experience in extracting the PDN model of PCB power rails and performing decoupling capacitor optimization, Loop inductance analysis is also necessary. Additionally, you should be able to analyze and review layout files related to Signal integrity and Power Integrity problems and provide practical solutions to the PCB design team based on simulation results and analysis. Strong knowledge of simulation tools, specifically Hspice, Power SI, Power DC, ADS, and other tools like Ansys SIwave, HFSS 3D, is preferred.,