Senior RTL Design Engineer Randstad Digital India
Randstad Digital India
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: RTL design, Microarchitecture, Digital Design, ASICs, Logic synthesis, Formal Verification, Power Estimation, STA, Documentation, OTP, MTP, I2C, Analog ICs, Clock Domain Crossing, Verification Test Planning, DFT Strategy, Post Layout Verification, Device Area, Power Evaluation, Efuse, controller design, Data Bus Handling, Register ReadWrite, DFT architecture, PMBus
About Randstad Digital India
Job Description
Job Description Principal Accountabilities: Minimum 8-15 yrs. Of Experience in RTL Design Develop micro-architecture and front-end digital design deliverables from concept to silicon with minimal supervision Develop digital functional blocks for various power management ASICs Lead optimized digital blocks design meeting functional and low power constraints and ensure spec compliance. Must have experience of defining Digital/Analog boundaries and digital design scope for Power Management ICs/Analog intensive ICs Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc. Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner. Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA. Verification test planning, feature extraction and verification test case development. Multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. Support DFT strategy and implementation. Interface with P & R for digital hand-off and post layout verification. Perform physical silicon device area and power evaluation where necessary. Produce high quality documentation for owned blocks. Develop work-around solutions where necessary to overcome device errata including documentation. Nice to Have Exposure of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions, DFT architecture and integration. Knowledge one or more Power Chip Communication I/Ps and protocols e.g. I2C, PMBUS etc. Qualifications Additional & Preferred Qualification Bachelors or masters degree in electrical/Electronic Engineering Micro-architecture, functional, test plan specification delivered according to project schedule RTL coding using Verilog/System Verilog First time right success rate Pro-actively taking ownership of responsibilities. Deliver work in the agreed timescales as set by program schedule for all assigned tasks.,