Senior Physical Design Lead Engineer ACL Digital
ACL Digital
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: synthesis, CTS, Floor Planning, clock tree synthesis, Clock Distribution, Extraction, timing closure, Physical verification, DFM, Perl, Full chip PnR, IO ring, multi voltage design, place route, Timing Convergence, IREM checks, signoff DRCLVS closure, power, signal integrity analysis, Automation Skills, Tcl, EDA toolspecific scripting
About ACL Digital
Job Description
You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,