Senior IO-MMU Verification Engineer ACL Digital
ACL Digital
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: UVM, SystemVerilog, AXI, PCIe, SVA, SMMU
About ACL Digital
Job Description
As a Senior IO-MMU Verification Engineer, you will be responsible for the functional verification of IO-MMU units, with a focus on translation, protection, and system interaction with DMA/IP blocks. Your key responsibilities will include developing UVM-based environments for IO-MMU verification, creating tests for virtual address translation, permissions, and fault injection, verifying compliance with protocols like PCIe ATS, PRI, and ARM SMMU, collaborating with SoC-level teams for system integration and validation, as well as driving functional and code coverage closure. To excel in this role, you should possess 8+ years of experience in the verification of memory or IO subsystems. Additionally, expertise in UVM, SystemVerilog, and SVA is required, along with strong debugging skills and protocol knowledge in AXI, PCIe, and SMMU. Experience with constrained-random and assertion-based verification, as well as familiarity with trace analysis and formal verification integration, will be advantageous.,