Senior IO-MMU RTL Design Engineer ACL Digital
ACL Digital
Office Location
Full Time
Experience: 8 - 8 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: RTL design, SystemVerilog, PCIe, timing closure, Memory protection, Address translation, SoC virtual memory systems, AXI protocols, Coherency, TLB, Page walk, IOVA mechanisms, FormalCDC tools
About ACL Digital
Job Description
You will be responsible for leading the design and integration of IO Memory Management Units (IO-MMUs) for secure, virtualized, and high-performance SoC architectures. Your key responsibilities will include architecting and implementing RTL for IO-MMU subsystems, defining IO translation and access control logic, collaborating with SoC, interconnect, and virtual memory teams, ensuring compliance with IOMMU standards (SMMU, PCIe ATS/PRI, RMRR), and delivering Lint, CDC, synthesis, and DFT clean designs. To excel in this role, you must possess at least 8 years of experience in SoC and IP-level RTL design. You should be proficient in SystemVerilog, with a strong understanding of memory protection and address translation. Experience with SoC virtual memory systems and PCIe/AXI protocols is required. Additionally, familiarity with coherency, TLB, page walk, and IOVA mechanisms, as well as skills in timing closure and formal/CDC tools, will be essential for success in this position.,