Senior Analog Layout Capgemini Engineering
Capgemini Engineering
Office Location
Full Time
Experience: 4 - 4 years required
Pay:
Salary Information not included
Type: Full Time
Location: Coimbatore
Skills: Analog Layout, Matching, EM, ESD, Shielding, EDA tools, PVS, Assura, MixedSignal layout design, LVSDRC debugging, Latchup, Parasitic, Short channel concepts, Cadence VLEVXL, Calibre DRC LVS
About Capgemini Engineering
Job Description
You have experience in Mixed-Signal layout design and hold a bachelor's degree. Your responsibilities will include working independently on block levels analog layout design from schematic, estimating the Area, optimizing Floorplan, Routing, and Verifications. You should have firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. It is essential to have good LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. You must possess a good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel concepts. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power, and area is crucial. You should be able to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve issues technically and professionally are required. Excellent communication is essential, along with being responsible for timely execution with a high quality of layout design. Primary Skills: - Analog Layout - Process or technology experience: TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm - EDA Tools: - Layout Editor: Cadence Virtuoso L, XL - Physical verification: DRC, LVS, Calibre Secondary Skills: - IO layout,