RTL Engineer UST
UST
Office Location
Full Time
Experience: 7 - 7 years required
Pay:
Salary Information not included
Type: Full Time
Location: Noida
Skills: RTL, PERL scripting, Verilog, RTL design, IP, SOC, Debugging, tcl scripting, Automation, SDC, SoC architecture, digital logic design, SYNOPSYS, Cadence, Mentor simulation tools, RTL logic synthesis, constraint writing, stdcells, IO blocks
About UST
Job Description
Hi All, please find the JD below:- RTL and PERL Scripting. We need more than 7-year experience candidate with following criteria. Expertise and hands on experience in Verilog/RTL design for IP or SoC. Command and thorough knowledge on digital logic design concepts. Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture. Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging skills. Desirable Pearl/TCL scripting and automation knowledge Desirable experience in RTL logic synthesis, sdc and constraint writing experience Understanding of basic soc architecture std-cells, IO blocks etc. Please share resume to jayalakshmi.r2@ust.com Regards. Jaya,