RTL Design Engineer ACL Digital
ACL Digital
Office Location
Full Time
Experience: 4 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Bangalore null, undefined
Skills: Python, devops, Cloud, problem-solving
About ACL Digital
Job Description
RTL Design Engineer
- Strong experience in RTL Design using Verilog/SystemVerilog
- Exposure to complex SoC/ASIC design and integration
- Hands-on with synthesis, Lint, CDC preferred
- Joining: Immediate to 20 days
Share resume at raksha.k@acldigital.com