Physical Design Engineers Mirafra Software Technologies
Mirafra Software Technologies
Office Location
Full Time
Experience: 2 - 2 years required
Pay:
Salary Information not included
Type: Full Time
Location: Noida
Skills: Floor Planning, CTS, Routing, static timing analysis, Spine, Perl, Python, Physical Design Engineer, Power Planning, Placement Optimization, Post route optimization, ECO implementation, DRC closure, PGGrid optimization, Adaptive PDN, custom clock tree, Htree, Multipoint CTS, Tcl
About Mirafra Software Technologies
Job Description
You are a Physical Design Engineer with 2-5 years of hands-on experience in different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. You should be well versed with high frequency design & advanced tech node implementation, in-depth understanding of PG-Grid optimization, custom clock tree design, and tackling high placement density/congestion bottlenecks. Your expertise should include identifying high vs low current density paths, layer/via optimization, and Adaptive PDN experience. You must have knowledge of custom clock tree designs such as H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Familiarity with PnR tool knobs/recipes for PPA optimization is essential. Experience in automation using Perl/Python and tcl is required. Good communication skills are necessary as you will be working in a cross-site cross-functional team environment. The ideal candidate will have a BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or an equivalent field with a minimum of 3 years of relevant experience. This is a great opportunity to be part of a fast-paced team responsible for delivering high-performance designs for high performance SoCs in sub-10nm process for the mobile space.,