Physical Design Engineer/Lead SoCtronics
SoCtronics
Office Location
Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: physical design, synthesis, Floor Planning, Parasitic Extraction, timing closure, Physical verification, DFM, Primetime, tcl scripting, PERL scripting, Power Planning, Place, Route, Clock Planning, Analog IP Integration, signal integrity analysis, DFY, Tapeout, Crosstalk Delay Analysis, Noise Glitch Analysis, Electrical Rules Analysis, Variations Analysis, Modeling Techniques, Synopsys ICC2
About SoCtronics
Job Description
You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,