Physical Design And Timing Engineer, Signoff Methodology Google

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Job Description

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in timing analysis and physical design. Experience in one or more scripting languages, such as Perl, TCL, Python. Preferred qualifications: Experience in physical design tool automation (e.g., synthesis, PandR). Experience in extraction of design parameters, QoR metrics and analyzing data trends. Experience in engineering across physical design and level implementation. Knowledge of parasitic extraction tools and flow. Knowledge of timing signoff conditions and parameters. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Drive the physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to push Power Performance Area (PPA) and yield. Analyze power performance area trade-offs across different methodologies and technologies. Work with cross-functional architecture, IPs, design, foundry, CAD and sign-off methodology teams. ,