Opening For FPGA Validation Engineers And Leads - Hyderabad UST
UST
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: DSO, Embedded C, RTL Coding, FPGA validation, PCIe 45, DDR 45, USB3, logic analyzers, ARM CortexM3, RISCV
About UST
Job Description
Hi All, FPGA validation engineers with experience in PCIe 4/5, DDR 4/5 or USB3 -Hands on experience working with DSO and Logic Analyzers -Leads and senior members need board level debugging knowledge -Some of the team members should be proficient with embedded c and RTL coding. -Basic knowledge on ARM Cortex-M3 or Risc-V will be helpful Please share your resume to jayalakshmi.r2@ust.com Regards, Jaya,