Memory & IO Layout Engineer UANDWE, Inc.
UANDWE, Inc.
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Control, Floor Planning, SRAM, cam, EDA tools, Cadence Virtuoso, Problem Solving, Communication skills, GPIO, DDR, LVDS, ESD, EM, LVS, DRC, ERC, Antenna, Density, foundries, Row Decoder, Io, pitched layout concepts, Compiler level integration, RF compiler memories, Mentor Graphics Caliber, logical reasoning, Custom layout development, HSTL, HCSL, VTMON, LVCMOS, Latchup, Litho Checks, ESDLU, CMOS functionality, CMOS fabrication process, 53FF technology
About UANDWE, Inc.
Job Description
Memory Layout Engineer: Location: Bangalore Experience: 3-7 Years Requirements Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories. Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology. Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. I/O Layout Design Engineer: Location: Bangalore Experience: 3-7 Years Roles & Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc., Need knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E, 5nm etc., SKILL: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required.,