Lead Physical Design Engineer Modernize Chip Solutions (MCS)
Modernize Chip Solutions (MCS)
Office Location
Full Time
Experience: 15 - 15 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: Calibre, Scripting, Automation, SoC Physical Design, FinFET node designs, Cadence, Synopsys PnR, STA tools
About Modernize Chip Solutions (MCS)
Job Description
Minimum 15+ Years of experience SoC Physical Design. Skills have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments /Feed through/ LFU Optimization/ Work hands-on to solve critical design and execution issues related to physical verification/implementation and sign-off. Expertise : Strong hands-on experience with Chip Level / Sub-chip level floor planning, Performing floor-planning and routing studies and implementation at block and full-chip level Push down the top-level floorplan and clock to Partition. partition, pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps. Closely working with Package team and reaching Die file milestones Location- Hyd/BLR Availability- Immediate to 60 days.,