FPGA Design Engineer Sr. Pretlist
Pretlist
Office Location
FULL TIME
Experience: 0 - 0 years required
Pay: 1 - 10001 /year
Type: FULL TIME
Location: India
Skills: 15-1132.00 Software Developers, Application
About Pretlist
Job Description
Pretlist powers secure mesh networks. We help businesses and governments communicate and navigate offline and without Carrier Networks.
If you are an FPGA Design Engineer with passion, then join our growing team. You will get a rare chance to craft Peer to Peer (P2P) applications that work offline. You dream it; you build it. Let’s build something big together.
Key Responsibilities
- Define and architect high-performance FPGA blocks that power our Software Defined Radios (SDR)
- Simulate and verify logic design for maximum throughput
Minimum Requirements
- BA, BS, or BE degree in Electrical Engineering, Computer Science, or a related field
- 6+ years of experience with RF design using Verilog or VHDL for Xilinx FPGAs
- Experience in Software Defined Radio (SDR)
- Experience with DSP flows on simulation software, including Vivado and MathWorks MATLAB, Simulink.
- Having knowledge of OFDM.
Generous Benefits
- You will join a global team that supports your professional dreams
- You will enjoy leave policies that promote your work-life balance
- We offer a great salary and benefits package