DFT Lead ACL Digital
ACL Digital
Office Location
Full Time
Experience: 6 - 6 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: Digital Design, ASIC design, scan insertion, Logic BIST, Scripting, DFT Verification, STA, static timing analysis, DFT Methodologies, ATPG Tools, Memory BIST, Test Compression Techniques, RTL Languages, Timing Constraints
About ACL Digital
Job Description
The ideal candidate for this position should possess a Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or a related field. You should have a strong understanding of digital design, ASIC design flow, and DFT methodologies. Your hands-on experience should include working with scan insertion & ATPG tools such as Synopsys DFT Compiler, Tetramax, Cadence Modus, as well as Memory BIST and Logic BIST. Additionally, you should be familiar with test compression techniques and have knowledge of RTL languages (Verilog, VHDL), scripting languages (TCL, Perl, Python), and DFT verification. It is essential that you have a good grasp of STA (Static Timing Analysis) and timing constraints related to DFT paths. The ideal candidate should have at least 6 years of experience in this field and should be available to join with any notice period.,