DFT Engineer Corpseed
Corpseed
Office Location
Full Time
Experience: 6 - 6 years required
Pay:
Salary Information not included
Type: Full Time
Location: Delhi
Skills: DFT, scan insertion, ATPG, DRC, SAF, Coverage analysis, Transition delay test coverage analysis, compression technique, manufacturing ATPG test patterns, stuckat, transition fault, TDF, Path Delay fault, onchip test compression techniques, Synopsis TetraMax, DFTMax, Cadence Encounter Test, MBIST insertion, Memory test validation, Mentor tools
About Corpseed
Job Description
Responsibilities DFT Engineer Bangalore, India 6+ years experience in DFT In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis Analyze design and propose best compression technique Debug and resolve the DRC issues Work with front end team to provide the solutions and make sure DFT DRCs are fixed Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is required In depth knowledge and hands on experience in MBIST insertion and Memory test validation Expertise in Mentor tools is plus Bachelors Degree in Electrical, Electronics or Computer Engineering,