Design For Test Perfectus Technology
Perfectus Technology
Office Location
Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Test Methodologies, SoCs, DFT, JTAG, static timing analysis, Formal Verification, Perl, Csh, sh, SystemOnChip designs, Memory BIST, SCANATPG, Mentor, Synopsys DFT tools, Verilog design, UNIX scripting languages, Tcl
About Perfectus Technology
Job Description
You should have experience in designing and implementing test methodologies for large, complex SoCs. You must be capable of resolving scan issues in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, and generating & integrating Memory BIST, JTAG, SCAN/ATPG. You should be an expert in analyzing fault coverage, delay fault, and enhancements. Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results is required. Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment is essential. Experience with static timing analysis (STA) & formal verification is desirable. Proficiency in common UNIX scripting languages (perl, tcl, csh, sh) is a must. Kindly email your resume to careers@perfectus.com with Job Code DFT in the subject line.,