Design Engineering Architech Cadence Design Systems
Cadence Design Systems
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Verilog, SystemVerilog, VHDL, RTL, DFT, Post, IST, Synthesis Automation, Timing Constraints, LBIST
About Cadence Design Systems
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL Design and implement RTL for DFT IP incl. POST, IST Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification Own and maintain, extend, and enhance existing DFT IP like LBIST Were doing work that matters. Help us solve what others cant.,