Data Parallel Accelerator Performance Intern Rivos

Our mission is to create computing platforms (HW/SW co-design) that will transform the industry with the most advanced technologies. As a DPA performance intern, you will be given a project to work on SOC-level performance per watt improvement through memory management innovations. You will be working with the internal SW (eg. OS, Kernel, Framework) and Silicon (eg. RTL, Power, Perf) team members Requirements - Knowledge in one or more of the following areas,  computer architecture , performance modeling, and analytical model - Knowledge and experience with common LLM (Large Language Model) workloads. - Proficiency in C or C++, and scripting languages such as Python. - Experience with high-level simulators for performance or power estimation is a plus. - Knowledge in server-class GPU/ML architecture is a plus. Responsibilities - Responsible for an analytical model implementation of LLM inference and training memory usage - Responsible for running the performance simulation to extract the workload's characteristics such as memory footprint and bandwidth requirement. - Responsible for evaluation ideas for performance improvement Minimum Education & Experience Current EE or CS master or Ph.D students with computer architecture backgrounds