Associate III - VLSI UST Global

About UST Global

Job Description

You will be responsible for executing small to mid-size customer projects in various fields of VLSI Frontend Backend or Analog design with minimal supervision. As an individual contributor, you will work on tasks related to RTL Design/Module and provide support to junior engineers in Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your successful and on-time completion of assigned tasks will contribute to the quality delivery approved by the project lead/manager. Your outcomes will be measured based on the quality of deliverables verified by the Lead/Manager, timely delivery as per relevant metrics, reduction in cycle time and cost through innovative approaches, number of trainings attended, and the number of new projects handled. You are expected to ensure the quality of deliverables by facilitating clean delivery of designs and modules for easy integration at the top level, meeting functional specifications and design guidelines without any deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines as requested and supporting the team lead in intermediate task delivery. Teamwork plays a significant role, requiring your participation in supporting team members/lead when needed and performing additional tasks in case any team member is unavailable. Embracing innovation and creativity, you should look to automate repeated tasks to save design cycle time, participate in technical discussions, and contribute to training forums. Your skills should include expertise in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, and Spice, among others. Proficiency in EDA Tools like Cadence, Synopsys, Mentor tool sets, and technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, and more is required. Familiarity with CMOS FinFet, FDSOI, technology, strong communication, analytical reasoning, problem-solving skills, and the ability to learn new skills are essential for successful project execution. Your knowledge should span across Frontend/Backend/Analog Design, project experience in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, understanding of design flow, methodologies, technical specifications, and the ability to execute assigned tasks effectively based on client/manager requirements. Having a command over digital logic design concepts, experience in large IP block design, knowledge of Synopsys/Cadence/Mentor simulation tools, Perl/TCL scripting, RTL logic synthesis, and basic SOC architecture will be advantageous for this role. Your attention to detail, technical skills, and ability to deliver tasks on time with quality are crucial aspects in contributing to the success of projects at UST.,