ASIC RTL Engineer 4+ Years Bangalore ACL Digital
ACL Digital
Office Location
Full Time
Experience: 4 - 4 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: Verilog, SystemVerilog
About ACL Digital
Job Description
RTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems. Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for different blocks within the ASIC.,