ASIC DFT Engineer Google
Google
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Python, DFT Methodologies, DFT Electronic Design Automation EDA tools, Tessent, Automatic Test Pattern Generation ATPG, Low power designs, BuiltIn Self Test BIST, Joint Test Action Group JTAG, Internal Joint Test Action Group IJTAG, Tcl
About Google
Job Description
As a DFT Engineer at Google, you will play a key role in developing custom silicon solutions for Google's direct-to-consumer products. Your expertise in DFT methodologies and Electronic Design Automation (EDA) tools like Tessent will contribute to the innovation and performance of products used by millions worldwide. Working closely with RTL and Physical Designer Engineers, you will help shape the next generation of hardware experiences. Your responsibilities will include working on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage and power domains. You will also be involved in writing basic scripts to automate the DFT flow and developing tests for production in the Automatic Test Equipment (ATE) flow. To be successful in this role, you should have a Bachelor's degree in Electrical or Electronics Engineering, along with at least 3 years of experience in DFT methodologies. Experience in areas such as ATPG, Low Power designs, BIST, JTAG, and IJTAG tools and flow will be beneficial. Preferred qualifications include experience in architecting/developing DFT flows and methodologies, as well as collaborating with Design, Physical Design (PD), and Static Timing Analysis (STA) teams. Strong scripting skills in languages like Python and TCL are also desired. Join us in our mission to organize the world's information and create helpful experiences for users through innovative hardware technologies. Your contributions will play a vital role in making people's lives better through technology.,